Design basis of combinational logic circuit 組合邏輯電路設計基礎
A combinational logic element having at least one input channel 一種至少有一個輸入通道的組合邏輯元件。
Combinational logic element 組合邏輯組件
Combinational logic circuit 組合邏輯電路
Combinational logic element 組合邏輯元件
Finally , we study two applications of bdd . the first one is the fault detect of combinational logic circuits 最后,研究了基于bdd的組合電路的故障檢測方法和基于bdd的網絡可靠度的計算方法等兩方面的應用。
Functions of logic synthesis are to transform and optimize the combinational logic functions and produce the pure logic level structural description 邏輯綜合的功能是對組合邏輯函數的描述進行轉換和優化,生成與邏輯功能描述等價的優化的邏輯級純結構描述。
The results of simulation prove that the improved algorithms are feasible for evolving the digital combinational logic circuits and improve the evolvable efficiency and convergence performance 仿真實驗結果證明了改進演化算法對于實現函數級數字組合邏輯電路的硬件演化是可行的,并且提高了演化算法的演化效率和收斂性能。
Digital design : binary system , boolean algebra , logic gates , simplification of boolean functions , combinational logic . analog design : amplifiers , frequency response , feedback , operational amplifier 數位設計:二進位制、布氏代數、邏輯閘、布氏函數的化簡、組合邏輯電路。類比設計:放大器、頻率響應、反饋系統、運算放大器。
Evolvable algorithms are applied to functional digital combinational logic circuits with the structure of classicepglo chip of altera co . and the detailed analyses of typical examples are also given 結合altera公司classicep610芯片的結構,研究了將演化算法應用于函數級數字組合邏輯電路的硬件演化,并且對典型實例進行了詳細分析。